Integrated circuit packages and their applications have undergone tremendous change in evolving to what is presently considered a contemporary design. Integrated circuit die (chip) sizes having increased dramatically, as have their operational clock rates. At the same time both the active and passive integrated circuit device dimensions have decreases. The circuit functions available from each integrated circuit die are now materially greater. As a consequence of such trends, integrated circuit packages require greater pin-out counts and higher power dissipation capabilities.
Numerous of the performance objectives were satisfied with ball grid array technology, including both the flip-chip and ceramic package variants. The power dissipation problem was addressed through the use of miniature heat sinks which attach directly to the flip-chip or ceramic package.
Simulation and testing of ball grid array type solder attachments involving silicon die or ceramic packages and underlying FR4 or the like fiberglass printed circuit boards has uncovered a susceptibility to stress failures. The failures occur with thermal cycling and are attributable to the materially different coefficients of thermal expansion. The stresses experienced by the ball grid array solder connections are aggravated with package size and with forces introduced by bonded or compressively affixed heat sinks. Moreover, the number of thermal stress cycles, and associated fatigue failure rates, have increased materially with the introduction of die power management techniques which frequently cycle the die between sleep and full operation modes.
A very new connection technology capable of managing the strain caused by the mismatch in coefficients of thermal expansion involves the use of solder columns, rather than solder balls, to define the electrical connections between the ceramic or die and the printed circuit board. Typical columns have an aspect ratio of approximately 9:2 and a nominal diameter of 0.020 inches. The solder columns are formed from high melting temperature solder using a nominal 90/10 alloy of lead to tin. The columns are first bonded to the ceramic or die, and thereafter attached to the printed circuit board using conventional low melting temperature solder paste reflow techniques.
As the power dissipation of flip-chip and ceramic packaged integrated circuits have increased, now often exceeding 50 watts, the heat sink has become critical necessity. Whether the heat sink is attached to the substrate by mechanical clamping, or by bonding, or the combination, the shock, vibration and pressure effects of heavy heat sinks are more than column array solder connections alone can support.
One approach to reinforcing the solder column connections of ceramic package substrates involves the placement of Kovar or Cusil pins in the corners of the ceramic packages to maintain the position of the ceramic package in relation to the printed circuit board in the presence of the heat sink vibrations and compressive forces. Such pins are attached to the ceramic substrate by brazing. The pins are then positioned into holes in the printed circuit board. Unfortunately, the use of such pins results in numerous additional and unique manufacturing steps. Furthermore, their use is effectively limited to ceramic packages, not for flip-chip die attachments.
In view of the foregoing, there exists a need for both structures and methods by which integrated circuits, whether in flip chip die or ceramic packages, can be attached through a solder column grid array adequately to support a heat sink.